1. Field of the Invention
The present invention relates to a memory device including a plurality of memory cells arranged in matrix form as a memory cell array in which a read word line and a write word line are adjacent in configuration to each other, and, relates to a coupling noise elimination method and a coupling noise eliminator for eliminating coupling noise generated between the adjacent read word line and write word line.
2. Description of the Related Art
There have been multi-port memories such as a register file, as the memory device according to the present invention, in which a write port is separated in configuration from a read port.
FIG. 1 is a circuit diagram showing a configuration of a memory cell array in a conventional memory device of 3 read/2 write in which a write port is separated in configuration from a read port. In FIG. 1. a memory cell comprises transfer gates 1 and 2 for inputting write-in data and a memory element 3 including inverters 31 and 32, and NMOS transistors 4 to 9 through which data stored in the memory element 3 are read out.
FIG. 2 is a block diagram showing a configuration of a register file including a plurality of the memory cells shown in FIG. 1. As shown in FIG. 2, the register file has the configuration of 32 entries/32 bits, and which comprises a memory cell array 100, an address decoder 12 for generating addresses to be transferred to the memory cell array 100, a readout data storing circuit 13 for storing data red from the memory cell array 100, and a write-in data storing circuit 14 for storing write-in data to be transferred to and written into the target memory cell in the memory cell array 100.
Next, a description will be given of the operation of the conventional memory device, namely, the register file shown in FIG. 2 with reference to a timing chart shown in FIG. 3.
The circuit elements such as the address decoder 12, the readout data storing circuit 13, the write-in data storing circuit 14 shown in FIG. 2 operate based on the clock supplied from outside.
In writing operation, the level of the write word line wrword0 designated by a write address wr0&lt;4:0&gt; shown in FIG. 2 becomes a High level (H level) when the clock is a Low level (L level). Thereby, the transfer gate 1 enters ON and the data (1 or 0) designated by the write bit line wrdata0 is transferred from the write-in data storing circuit 14 to the memory element 13 through the transfer gate 1.
In reading operation, the level of the read word line rdword0 designated by the read address rd0&lt;4:0&gt; shown in FIG. 2 becomes the H level when the clock CLK is the H level. Thereby, the NMOS transistor 4 enters ON and the data (1 or 0) stored in the memory element 3 is read and then transferred to the readout data storing circuit 12 through the NMOS transistor 5 and the read bit line rdword0.
In the configuration of the memory cell shown in FIG. 1, both the read word line rdword0 and the write word line wrword0 are adjacent to each other. FIG. 4 shows the detailed configuration of a word (each word has 32 memory cells) in the memory cell array of 32 words.times.32 bits in which the read word line rdword0 and the write word line wrword0 which are adjacent to each other. In this configuration, when the level of the write word line rdword0 is switched to the H level, the level of the read word line rdword0 is slightly raised in voltage level associated with the coupling capacitance Cc between the read word line rdword0 and the write word line wrword0 as shown at the timing T11 in FIG. 5. Because the change of the write word line wrword0 is a static process, the level of the write word line wrword0 is then shifted and fixed to, as the time proceeds, the L level as shown at the timing T12 in FIG. 5.
Recent advances in the state of the semiconductor fabrication art, namely, advanced semiconductor technologies in high speed and low voltage decrease a threshold voltage Vth in MOS transistors forming memory devices. In addition, the distance between adjacent signal lines in the semiconductor memory devices becomes narrow according to the progress of the miniaturization of LSI devices.
Accordingly, when the voltage which is temporarily generated in the write word line wrword0 is over the threshold voltage of the NMOS transistor as the transfer gate 1 for write-in data, the data "0" on the wrire word line wrword0 is written into the memory element 3 in the memory cell array 100, as shown by the reference character "(A)" in FIG. 5. This causes writing error.
A description will be given of the mechanism of writing error based on equations.
The kinds of capacitances generated on the writ word line wrword0 are as follows:
(1) A coupling capacitance Cc1 between the read word line rdword0 and the write word line wrword0; PA1 (3) A capacitance Cs between the write word line wrword0 and a substrate; and PA1 (4) A gate capacitance Cg of a NOS transistor connected to the write word line wrword0.
(2) A coupling capacitance Cc2 between the write word lines wrword1 and wrword0;
In the following calculation, the capacitance Cg indicated by the case (4) can be neglected for simple calculation.
Recent miniaturization of LSI devices causes that the coupling capacitance Cc becomes equal to the capacitance Cs of the substrate. In general, the coupling capacitance Cc1 becomes equal to the coupling capacitance Cc2 because the wiring distance in the word lines has the minimum value.
When Cc=Cs and Cc1=Cc2, the coupling noise voltage by which the write word line wrword0 is raised is as follows: EQU Coupling noise voltage=(Cc/(Cc+Cs)).multidot.Vdd=Vdd/2.
For example, the coupling noise voltage becomes 1.0V when Vdd=2.0V.
When the wiring resistance of the word line is R[Ohm], the voltage level of the write word line wrword0 is raised to the coupling noise voltage of 1.0V during the rising time period (2Cc+Cs).multidot.R of the read word line rdword0.
After this, because the voltage level of the write word line wrword0 is fallen to the L level during the time interval (2Cc+Cs).multidot.a R, the waveform of the voltage level of the write word line wrword0 can be shown by FIG. 6.
When the threshold voltage of the NMOS transistor as the transfer gate for write-in data is 0.4V, the following equation can be satisfied:
Coupling noise voltage=1.0V&gt;Threshold voltage Vth (=0.4V) of the NMOS transistor as the transfer gate. Accordingly, the writing error happens because the NMOS transistor as the transfer gate 1 enters ON.
This kind of the coupling capacitance is also generated in the following case. As shown in FIG. 7, a coupling capacitance is generated in the read word line reword0 when the voltage level of the write word line wrword0 is changed to the H level at the timing T13. Thereby, the NMOS transistor 4 enters ON in spite of the data reading and a data item is then read from the memory element 3. This is the reading error.